The present invention relates to a method and/or architecture for generating technology files for hardmacros generally and, more particularly, to a method and/or architecture for generating technology and/or timing files for traditional hardmacros as well as hierarchical hardmacros (HHMs) and cores.
Conventional layout tools (i.e., Avant!(copyright) Corporation Avant! Apollo-II(trademark), Discovery(trademark), Mars(trademark), Saturn(trademark), etc.) generate hardmacro (hardmac) files for placement and routing layout information for integrated circuit designs. Conventional hardmac generator tools fail to provide one or more of the following features: (i) accurate prediction of repeater insertion into the layout, (ii) transportable file formats or syntax (i.e., files that are generated in formats or syntax that can be read and/or processed by other synthesis/layout/analysis tools that are implemented simultaneously with and/or subsequent to the hardmac generation tools), (iii) accurate delay and/or slack calculation, and/or (iv) hardmacro generation for skeleton, register-transfer-level (RTL) and/or full gate (FGN) netlist based flows.
It would be desirable to have a hardmac development tool that provides accurate skeleton, RTL, and/or FGN netlist technology files for hardmacro files in one or more transportable file formats.
The present invention concerns a method for generating one or more hardmacro technology files comprising the steps of determining a netlist, generating a timing constraints file in response to (i) the netlist and (ii) a time budget, and generating the hardmacro technology files in response to (i) the netlist and (ii) the timing constraints file.
The objects, features and advantages of the present invention include providing a hardmac technology file and/or timing file generation tool that may provide (i) accurate die size estimates, (ii) accurate prediction of repeater insertion into the layout, (iii) transportable language or syntax (e.g., hardmacro and/or clock timing files generated in formats or syntax that can be read and/or processed by other synthesis/layout/analysis tools), (iv) accurate delay and/or slack calculation, and/or (v) hardmacro generation for skeleton, register-transfer-level (RTL) and/or full gate (FGN) netlist based flows.